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preliminary 2m x 36/4m x 18/1m x 72 flow-through sram with nobl? architecture cy7c1471v33 cy7c1473v33 cy7c1475v33 cypress semiconductor corporation 3901 north first street san jose , ca 95134 408-943-2600 document #: 38-05288 rev. *a revised january 27, 2003 features ? zero bus latency, no dead cycles between write and read cycles supports 133-mhz bus operations 2m 36/4m 18/1m 72 common i/o fast clock-to-output times ? 5.5 ns (for 150-mhz device) ? 6.5 ns (for 133-mhz device) ? 7.5 ns (for 117-mhz device) ? 8.5 ns (for 100-mhz device) single 3.3v ?5% and +5% power supply v dd separate v ddq for 3.3v or 2.5v clock enable (cen ) pin to suspend operation burst capability?linear or interleaved burst order available in 119-ball bump bga and 100-pin tqfp packages (cy7c1471v33 and cy7c1473v33) 165-ball fbga and 209-ball bga(cy7c1475v33) packages are offered by opportunity basis. (please contact cypress sales or marketing functional description the cy7c1471v33, cy7c1473v33, and cy7c1475v33 srams are designed to eliminate dead cycles when transi- tions from read to write or vice versa. these srams are optimized for 100 percent bus utilization and achieves zero bus latency. they integrate 2,097,152 36/4,194,304 18/ 1,048,576 72 sram cells, respectively, with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. the synchronous burst sram family employs high-speed, low-power cmos designs using advanced single layer polysilicon, three-layer metal technology. each memory cell consists of six transistors. all synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (clk). the synchronous inputs include all addresses, all data inputs, depth-expansion chip enables (ce 1 , ce 2 , and ce 3 ), cycle start input (adv/ld ), clock enable (cen ), byte write selects (bws a , bws b , bws c , bws d , bws e , bws f , bws g , bws h ), and read-write control (we ). bws c and bws d apply to cy7c1471v33 and cy7c1475v33 only. bws e , bws f , bws g , and bws h apply to cy7c1475v33 only. a clock enable (cen ) pin allows operation of the cy7c1471v33, cy7c1473v33, and cy7c1475v33 to be suspended as long as necessary. all synchronous inputs are ignored when (cen ) is high and the internal device registers will hold their previous values. there are three chip enable (ce 1 , ce 2 , ce 3 ) pins that allow the user to deselect the device when desired. if any one of these three are not active when adv/ld is low, no new memory operation can be initiated and any burst cycle in progress is stopped. however, any pending data transfers (read or write) will be completed. the data bus will be in high-impedance state two cycles after chip is deselected or a write cycle is initiated. the cy7c1471v33, cy7c1473v33, and cy7c1475v33 have an on-chip two-bit burst counter. in the burst mode, cy7c1471v33, cy7c1473v33, and cy7c1475v33 provide four cycles of data for a single address presented to the sram. the order of the burst sequence is defined by the mode input pin. the mode pin selects between linear and interleaved burst sequences. the adv/ld signal is used to load a new external address (adv/ld = low) or increment the internal burst counter (adv/ld = high). output enable (oe ) and burst sequence select (mode) are the asynchronous signals. oe can be used to disable the outputs at any given time. zz may be tied to low if it is not used. four pins are used to implement jtag test capabilities. the jtag circuitry is used to serially shift data to and from the device. jtag inputs use lvttl/lvcmos levels to shift data during this testing mode of operation. clk a x cen we bws x ce 1 ce ce 2 oe 2m 36/ memory array logic block diagram dq x data-in reg. q d ce control and write logic 3 adv/ld mode dp x 4m 18/ 1m 72 2m 36 4m 18 a x dq x dp x bws x x = 20:0 x = 21:0 x = a, b x= a, b, 1m 72 x = 19:0 x = a, b, c, d x = a, b, c, d c, d x = a, b x = a, b x = a, b, c,d,e,f,g,h x = a, b, c,d,e,f,g,h c,d,e,f,g,h x = a, b,
preliminary cy7c1471v33 cy7c1473v33 cy7c1475v33 document #: 38-05288 rev. *a page 2 of 26 pin configurations selection guide cy7c1471v33-150 cy7c1473v33-150 cy7c1475v33-150 cy7c1471v33-133 cy7c1473v33-133 cy7c1475v33-133 cy7c1471v33-117 cy7c1473v33-117 cy7c1475v33-117 cy7c1471v33-100 cy7c1473v33-100 cy7c1475v33-100 unit maximum access time 5.5 6.5 7.5 8.5 ns maximum operating current tbd tbd tbd tbd ma maximum cmos standby current tbd tbd tbd tbd ma shaded area contains advanced information. a a a a a 1 a 0 nc nc v ss v dd a a a a a a v ddq v ss dqb dqb dqb v ss v ddq dqb dqb v ss nc v dd dqa dqa v ddq v ss dqa dqa v ss v ddq v ddq v ss dqc dqc v ss v ddq dqc dqc v dd v ss dqd dqd v ddq v ss dqd dqd dqd v ss v ddq a a ce 1 ce 2 bws a ce 3 v dd v ss clk we cen oe a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 a a adv/ld zz cy7c1471v33 100-pin tqfp packages a a a a a 1 a 0 nc nc v ss v dd a a a a a a a nc nc v ddq v ss nc dpa dqa dqa v ss v ddq dqa dqa v ss nc v dd dqa dqa v ddq v ss dqa dqa nc nc v ss v ddq nc nc nc nc nc nc v ddq v ss nc nc dqb dqb v ss v ddq dqb dqb nc v dd v ss dqb dqb v ddq v ss dqb dqb dpb nc v ss v ddq nc nc nc a a ce 1 ce 2 nc nc bws b bws a ce 3 v dd v ss clk we cen oe a a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 a a adv/ld zz mode a bws d mode bws c dqc dqc dqc dqc dpc dqd dqd dpd dqd nc dpb dqb dqa dqa dqa dqa dpa dqb dqb (2m 36) cy7c1473v33 bws b nc nc a a a a (4m 18)
preliminary cy7c1471v33 cy7c1473v33 cy7c1475v33 document #: 38-05288 rev. *a page 3 of 26 pin configurations (continued) 234567 1 a b c d e f g h j k l m n p r t u dq a v ddq nc nc dq c dq d dq c dq d aa aa av ddq ce2 a v ddq v ddq v ddq v ddq nc nc a dq c dq c dq d dq d tms v dd a a dp d a a adv/ld a ce 3 nc v dd aanc v ss v ss nc dp b dq b dq b dq a dq b dq b dq a dq a nc tdi tdo v ddq tck v ss v ss v ss nc v ss v ss v ss v ss mode ce 1 v ss oe v ss v ddq bws c a v ss we v ddq v dd nc v dd v ss clk nc bws a cen v ss v ddq v ss zz nc a a a1 a0 v ss v dd nc cy7c1471v33 (2m 36) ? 7 17 bga dp c dq b aa dq c dq b dq c dq c dq c dq b dq b dq a dq a dq a dq a dp a dq d dq d dq d dq d bws d 119-ball bump bga bws b 234567 1 a b c d e f g h j k l m n p r t u a dq a v ddq nc nc nc dq b dq b dq b dq b aa aa av ddq ce2 a nc v ddq nc v ddq v ddq v ddq nc nc nc a a dq b dq b dq b dq b nc nc nc nc tms v dd a a dp b a a adv/ld a ce 3 nc v dd aanc v ss v ss nc nc dp a dq a dq a dq a dq a dq a dq a dq a nc tdi tdo v ddq tck v ss v ss v ss nc v ss v ss v ss v ss v ss mode ce 1 v ss nc oe v ss v ddq bws b av ss nc v ss we nc v ddq v dd nc v dd nc v ss clk nc nc bws a cen v ss nc v ddq v ss nc zz nc a a a a1 a0 v ss nc v dd nc cy7c1473v33 (4m 18) ? 7 17 bga
preliminary cy7c1471v33 cy7c1473v33 cy7c1475v33 document #: 38-05288 rev. *a page 4 of 26 pin configurations (continued) cy7c1471v33 (2m 36) ? 11 15 fbga 165-ball bump fbga (this package is offered by opportunity basis) cy7c1473v33 (4m 18) ? 11 15 fbga 234567 1 a b c d e f g h j k l m n p r tdo nc nc nc nc dp b nc dq b ace 1 nc ce 3 bws b cen a ce2 nc dq b dq b mode nc dq b dq b nc nc nc a a v ddq nc bws a clk we v ss v ss v ss v ss v ddq v ss v dd v ss v ss v ss nc v ss v ss v ss v ss v ddq v ddq nc v ddq v ddq v ddq v ddq a a v dd v ss v dd v ss v ss v ddq v dd v ss v dd v ss v dd v ss v ss v ss v dd v dd v ss v dd v ss v ss nc tck a0 v ss atdi atms dq b v ss nc v ss dq b nc v dd v ss v ss v ss v ss nc v ss a1 dq b nc nc nc v ddq v ss 891011 nc aa adv/ld a oe a a 144m v ss v ddq nc dp a v ddq v dd nc dq a dq a nc nc nc dq a nc v dd v ddq v dd v ddq dq a v dd nc v dd nc v dd v ddq dq a v ddq v dd v dd v ddq v dd v ddq nc v ddq a a v ss aa aa dq a nc nc zz dq a nc nc dq a a v ddq 234567 1 a b c d e f g h j k l m n p r tdo nc nc dp c dq c dp d nc dq d ace 1 bws b ce 3 bws c cen a ce2 dq c dq d dq d mode nc dq c dq c dq d dq d dq d a a v ddq bws d bws a clk we v ss v ss v ss v ss v ddq v ss v dd v ss v ss v ss nc v ss v ss v ss v ss v ddq v ddq nc v ddq v ddq v ddq v ddq a a v dd v ss v dd v ss v ss v ddq v dd v ss v dd v ss v dd v ss v ss v ss v dd v dd v ss v dd v ss v ss nc tck a0 v ss atdi atms dq c v ss dq c v ss dq c dq c v dd v ss v ss v ss v ss nc v ss a1 dq d dq d nc nc v ddq v ss 891011 nc aa adv/ld nc oe a a 144m v ss v ddq nc dp b v ddq v dd dq b dq b dq b nc dq b nc dq a dq a v dd v ddq v dd v ddq dq b v dd nc v dd dq a v dd v ddq dq a v ddq v dd v dd v ddq v dd v ddq dq a v ddq a a v ss aa aa dq b dq b dq b zz dq a dq a dp a dq a a v ddq
preliminary cy7c1471v33 cy7c1473v33 cy7c1475v33 document #: 38-05288 rev. *a page 5 of 26 pin configurations (continued) a b c d e f g h j k l m n p r t u v w 123456789 11 10 dqg dqg dqg dqg dqg dqg dqg dqg dqc dqc dqc dqc nc dpg dqh dqh dqh dqh dqd dqd dqd dqd dpd dpc dqc dqc dqc dqc nc dqh dqh dqh dqh dph dqd dqd dqd dqd dqb dqb dqb dqb dqb dqb dqb dqb dqf dqf dqf dqf nc dpf dqa dqa dqa dqa dqe dqe dqe dqe dpa dpb dqf dqf dqf dqf nc dqa dqa dqa dqa dpe dqe dqe dqe dqe aa aa nc nc nc aa nc a aa aa a a1 a0 a aa aa a nc nc nc nc nc nc bws b bws f bws e bws a bws c bws g bws d bws h tms tdi tdo tck nc nc mode nc cen v ss nc clk nc v ss v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v ss v ss v ss v ss v ss v ss v ss v ss nc v dd nc oe ce 3 ce 1 ce 2 adv/ld we v ss v ss v ss v ss v ss v ss v ss zz v ss v ss v ss v ss nc v ddq v ss v ss nc v ss v ssq v ss v ss v ss v ss nc v ss v ddq v ddq v ddq v ddq v ddq nc v ddq v ddq v ddq v ddq nc v ddq v ddq v ddq v ddq nc v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq cy7c1475v33 (1m 72) 209-ball bga (this package is offered by opportunity basis) pin definitions pin name i/o type pin description a0 a1 a input- synchronous address inputs used to select one of the 2097152/4194304/1048576 address locations . sampled at the rising edge of the clk. bws a bws b bws c bws d bws e bws f bws g bws h input- synchronous byte write select inputs, active low . qualified with we to conduct writes to the sram. sampled on the rising edge of clk. bws a controls dq a and dp a , bws b controls dq b and dp b , bws c controls dq c and dp c , bws d controls dq d and dp d .bws e controls dq e and dp e , bws f controls dq f and dp f , bws g controls dq g and dp g , bws h controls dq h and dp h . we input- synchronous write enable input, active low . sampled on the rising edge of clk if cen is active low. this signal must be asserted low to initiate a write sequence.
preliminary cy7c1471v33 cy7c1473v33 cy7c1475v33 document #: 38-05288 rev. *a page 6 of 26 adv/l d input- synchronous advance/load input used to advance the on-chip address counter or load a new address . when high (and cen is asserted low) the internal burst counter is advanced. when low, a new address can be loaded into the device for an access. after being deselected, adv/ld should be driven low in order to load a new address. clk input-clock clock input . used to capture all synchronous inputs to the device. clk is qualified with cen . clk is only recognized if cen is active low. ce 1 input- synchronous chip enable 1 input, active low . sampled on the rising edge of clk. used in conjunction with ce 2 and ce 3 to select/deselect the device. ce 2 input- synchronous chip enable 2 input, active high . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 3 to select/deselect the device. ce 3 input- synchronous chip enable 3 input, active low . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 2 to select/deselect the device. oe input- asynchronous output enable, active low . combined with the synchronous logic block inside the device to control the direction of the i/o pins. when low, the i/o pins are allowed to behave as outputs. when deasserted high, i/o pins are three-stated, and act as input data pins. oe is masked during the data portion of a write sequence, during the first clock when emerging from a deselected state and when the device has been deselected. cen input- synchronous clock enable input, active low . when asserted low the clock signal is recognized by the sram. when deasserted high the clock signal is masked. since deasserting cen does not deselect the device, cen can be used to extend the previous cycle when required. dq a dq b dq c dq d dq e dq f dq g dq h i/o- synchronous bidirectional data i/o lines . as inputs, they feed into an on-chip data register that is triggered by the rising edge of clk. as outputs, they deliver the data contained in the memory location specified by a [x:0] during the previous clock rise of the read cycle. the direction of the pins is controlled by oe and the internal control logic. when oe is asserted low, the pins can behave as outputs. when high, dq a ? dq d are placed in a three-state condition. the outputs are automatically three-stated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of oe . dq a,b,c,d,e,f,g, and h are eight bits wide dp a dp b dp c dp d dp e dp f dp g dp h i/o- synchronous bidirectional data parity i/o lines . functionally, these signals are identical to dq [x:0]. dp a,b,c,d,e,f,g, and h are one bit wide. zz input- asynchronous zz ? sleep ? input . this active high input places the device in a non-time critical ? sleep ? condition with data integrity preserved. mode input strap pin mode input . selects the burst order of the device. tied high selects the interleaved burst order. pulled low selects the linear burst order. mode should not change states during operation. when left floating mode will default high, to an interleaved burst order. v dd power supply power supply inputs to the core of the device . v ddq i/o power supply power supply for the i/o circuitry . v ss ground ground for the device . should be connected to ground of the system. tdo jtag serial output synchronous serial data-out to the jtag circuit . delivers data on the negative edge of tck (bga only). tdi jtag serial input synchronous serial data-in to the jtag circuit . sampled on the rising edge of tck (bga only). tms test mode select synchronous this pin controls the test access port state machine . sampled on the rising edge of tck (bga only). tck jtag serial clock serial clock to the jtag circuit . (bga only.) 144m ? nc. this pin is reserved for expansion to 144 mb. nc ? no connects . pin definitions (continued) pin name i/o type pin description
preliminary cy7c1471v33 cy7c1473v33 cy7c1475v33 document #: 38-05288 rev. *a page 7 of 26 introduction functional overview the cy7c1471v33/cy7c1473v33/cy7c1475v33 is a synchronous flow-through burst nobl sram designed specifically to eliminate wait states during write-read transi- tions. all synchronous inputs pass through input registers controlled by the rising edge of the clock. the clock signal is qualified with the clock enable input signal (cen ). if cen is high, the clock signal is not recognized and all internal states are maintained. all synchronous operations are qualified with cen . maximum access delay from the clock rise (t cdv ) is 5.5 ns (150-mhz device). accesses can be initiated by asserting chip enable(s) (ce 1 , ce 2 , ce 3 on the tqfp, ce 1 on the bga) active at the rising edge of the clock. if clock enable (cen ) is active low and adv/ld is asserted low, the address presented to the device will be latched. the access can either be a read or write operation, depending on the status of the write enable (we ). byte write selects can be used to conduct byte write opera- tions. write operations are qualified by the write enable (we ). all writes are simplified with on-chip synchronous self-timed write circuitry synchronous chip enable (ce 1 , ce 2 , and ce 3 on the tqfp, ce 1 on the bga) and an asynchronous output enable (oe ) simplify depth expansion. all operations (reads, writes, and deselects) are pipelined. adv/ld should be driven low once the device has been deselected in order to load a new address for the next operation. single read accesses a read access is initiated when the following conditions are satisfied at clock rise: (1) cen is asserted low, (2) ce 1 , ce 2 , and ce 3 are all asserted active, (3) the write enable input signal we is deasserted high, and 4) adv/ld is asserted low. the address presented to the address inputs is latched into the address register and presented to the memory core and control logic. the control logic determines that a read access is in progress and allows the requested data to propagate to the output buffers. the data is available within 5.5 ns (150-mhz device) provided oe is active low. after the first clock of the read access the output buffers are controlled by oe and the internal control logic. oe must be driven low in order for the device to drive out the requested data. on the subsequent clock, another operation (read/write/deselect) can be initiated. when the sram is deselected at clock rise by one of the chip enable signals, its output will be three-stated immediately. burst read accesses the cy7c1471v33/cy7c1473v33/cy7c1475v33 has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four reads without reasserting the address inputs. adv/ld must be driven low in order to load a new address into the sram, as described in the single read accesses section above. the sequence of the burst counter is determined by the mode input signal. a low input on mode selects a linear burst mode, a high selects an interleaved burst sequence. both burst counters use a0 and a1 in the burst sequence, and will wrap-around when incre- mented sufficiently. a high input on adv/ld will increment the internal burst counter regardless of the state of chip enables inputs or we . we is latched at the beginning of a burst cycle. therefore, the type of access (read or write) is maintained throughout the burst sequence. single write accesses write access are initiated when the following conditions are satisfied at clock rise: (1) cen is asserted low, (2) chip enable(s) asserted active, and (3) the write signal we is asserted low. the address presented is loaded into the address register. the write signals are latched into the control logic block. the data lines are automatically three-stated regardless of the state of the oe input signal. this allows the external logic to present the data on dq and dp. on the next clock rise the data presented to dq and dp (or a subset for byte write operations, see write cycle description table for details) inputs is latched into the device and the write is complete. additional accesses (read/write/deselect) can be initiated on this cycle. the data written during the write operation is controlled by byte write select signals. the cy7c1471v33/ cy7c1473v33/cy7c1475v33 provide byte write capability that is described in the write cycle description table. asserting the write enable input (we ) with the selected byte write select input will selectively write to only the desired bytes. bytes not selected during a byte write operation will remain unaltered. a synchronous self-timed write mechanism has been provided to simplify the write operations. byte write capability has been included in order to greatly simplify read/modify/write sequences, which can be reduced to simple byte write operations. because the cy7c1471v33/cy7c1473v33/cy7c1475v33 are common i/o devices, data should not be driven into the device while the outputs are active. the output enable (oe ) can be deasserted high before presenting data to the dq and dp inputs. doing so will three-state the output drivers. as a safety precaution, dq and dp are automatically three-stated during the data portion of a write cycle, regardless of the state of oe . burst write accesses the cy7c1471v33/cy7c1473v33/cy7c1475v33 has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four write operations without reasserting the address inputs. adv/ld must be driven low in order to load the initial address, as described in the single write access section above. when adv/ld is driven high on the subsequent clock rise, the chip enables (ce 1 , ce 2 , and ce 3 ) and we inputs are ignored and the burst counter is incremented. the correct bws a,b,c,d,e,f,g,h / bws a,b,c,d /bws a,b inputs must be driven in each cycle of the burst write in order to write the correct bytes of data.
preliminary cy7c1471v33 cy7c1473v33 cy7c1475v33 document #: 38-05288 rev. *a page 8 of 26 sleep mode the zz input pin is an asynchronous input. asserting zz places the sram in a power conservation ? sleep ? mode. two clock cycles are required to enter into or exit from this ? sleep ? mode. while in this mode, data integrity is guaranteed. accesses pending when entering the ? sleep ? mode are not considered valid nor is the completion of the operation guaranteed. the device must be deselected prior to entering the ? sleep ? mode. ce s must remain inactive for the duration of t zzrec after the zz input returns low. cycle description truth table [1, 2, 3, 4, 5, 6] operation address used ce cen adv/ld we bws x clk comments deselected external 1 0 0 x x l-h i/os three-state following next recognized clock. suspend ? x 1 x x x l-h clock ignored, all operations suspended. begin read external 0 0 0 1 x l-h address latched. begin write external 0 0 0 0 valid l-h address latched, data presented two valid clocks later. burst read operation internal x 0 1 x x l-h burst read operation. previous access was a read operation. addresses incremented internally in conjunction with the state of mode. burst write operation internal x 0 1 x valid l-h burst write operation. previous access was a write operation. addresses incremented internally in conjunction with the state of mode. bytes written are determined by bws a,b,c,d,e,f,g,h / bws a,b,c,d /bws a,b . interleaved burst sequence first address second address third address fourth address a[1:0] a[1:0] a[1:0] a[1:0] 00 -01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 linear burst sequence first address second address third address fourth address a[1:0] a[1:0] a[1:0] a[1:0] 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 parameter description test conditions min. max. unit i ddzz snooze mode standby current zz > v dd ? 0.2v 15 ma t zzs device operation to zz zz > v dd ? 0.2v 2t cyc ns t zzrec zz recovery time zz < 0.2v 2t cyc ns notes: 1. x = ? don ? t care, ? 1 = logic high, 0 = logic low, ce stands for all chip enables active. bws x = 0 signifies at least one byte write select is active, bws x = valid signifies that the desired byte write selects are asserted, see write cycle description table for details. 2. write is defined by we and bws x . see write cycle description table for details. 3. the dq and dp pins are controlled by the current cycle and the oe signal. 4. cen = 1 inserts wait states. 5. device will power-up deselected and the i/os in a three-state condition, regardless of oe . 6. oe assumed low.
preliminary cy7c1471v33 cy7c1473v33 cy7c1475v33 document #: 38-05288 rev. *a page 9 of 26 ieee 1149.1 serial boundary scan (jtag) the cy7c1471v33/cy7c1473v33/cy7c1475v33 incorpo- rates a serial boundary scan test access port (tap) in the bga package only. the tqfp package does not offer this functionality. this port operates in accordance with ieee standard 1149.1-1900, but does not have the set of functions required for full 1149.1 compliance. these functions from the ieee specification are excluded because their inclusion places an added delay in the critical speed path of the sram. note that the tap controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant taps. the tap operates using jedec standard 3.3v i/o logic levels. disabling the jtag feature it is possible to operate the sram without using the jtag feature. to disable the tap controller, tck must be tied low (v ss ) to prevent clocking of the device. tdi and tms are inter- nally pulled up and may be unconnected. they may alternately be connected to v dd through a pull-up resistor. tdo should be left unconnected. upon power-up, the device will come up in a reset state which will not interfere with the operation of the device. test access port ? test clock the test clock is used only with the tap controller. all inputs are captured on the rising edge of tck. all outputs are driven from the falling edge of tck. note: 7. bwsx represents any byte write signal bw[0..7]. to enable any byte write bwsx, a low logic signal should be applied at clock rise. any number of byte writes can be enabled at the same time for any given write. write cycle descriptions [1, 2] function (cy7c1471v33) we bws d bws c bws b bws a read 1xxxx write ? no bytes written 01111 write byte 0 ? (dq a and dp a) 01110 write byte 1 ? (dq b and dp b) 01101 write bytes 1, 0 01100 write byte 2 ? (dq c and dp c) 01011 write bytes 2, 0 01010 write bytes 2, 1 01001 write bytes 2, 1, 0 01000 write byte 3 ? (dq d and dp d) 00111 write bytes 3, 0 00110 write bytes 3, 1 00101 write bytes 3, 1, 0 00100 write bytes 3, 2 00011 write bytes 3, 2, 0 00010 write bytes 3, 2, 1 00001 write all bytes 00000 function (cy7c1473v33) we bws b bws a read 1xx write ? no bytes written 011 write byte 0 ? (dq a and dp a) 010 write byte 1 ? (dq b and dp b) 001 write both bytes 000 function (cy7c1475v33) [7] we bws x read 1x write byte x 0 0 write all bytes 0 all bw s = 0
preliminary cy7c1471v33 cy7c1473v33 cy7c1475v33 document #: 38-05288 rev. *a page 10 of 26 test mode select the tms input is used to give commands to the tap controller and is sampled on the rising edge of tck. it is allowable to leave this pin unconnected if the tap is not used. the pin is pulled up internally, resulting in a logic high level. test data-in (tdi) the tdi pin is used to serially input information into the registers and can be connected to the input of any of the registers. the register between tdi and tdo is chosen by the instruction that is loaded into the tap instruction register. for information on loading the instruction register, see the tap controller state diagram. tdi is internally pulled up and can be unconnected if the tap is unused in an application. tdi is connected to the most significant bit (msb) on any register. test data-out (tdo) the tdo output pin is used to serially clock data-out from the registers. the output is active depending upon the current state of the tap state machine (see tap controller state diagram). the output changes on the falling edge of tck. tdo is connected to the least significant bit (lsb) of any register. performing a tap reset a reset is performed by forcing tms high (v dd ) for five rising edges of tck. this reset does not affect the operation of the sram and may be performed while the sram is operating. at power-up, the tap is reset internally to ensure that tdo comes up in a high-z state. tap registers registers are connected between the tdi and tdo pins and allow data to be scanned into and out of the sram test circuitry. only one register can be selected at a time through the instruction registers. data is serially loaded into the tdi pin on the rising edge of tck. data is output on the tdo pin on the falling edge of tck. instruction register three-bit instructions can be serially loaded into the instruction register. this register is loaded when it is placed between the tdi and tdo pins as shown in the tap controller block diagram. upon power-up, the instruction register is loaded with the idcode instruction. it is also loaded with the idcode instruction if the controller is placed in a reset state as described in the previous section. when the tap controller is in the captureir state, the two least significant bits are loaded with a binary ? 01 ? pattern to allow for fault isolation of the board level serial test path. bypass register to save time when serially shifting data through registers, it is sometimes advantageous to skip certain states. the bypass register is a single-bit register that can be placed between tdi and tdo pins. this allows data to be shifted through the sram with minimal delay. the bypass register is set low (v ss ) when the bypass instruction is executed. boundary scan register the boundary scan register is connected to all the input and output pins on the sram. several no connect (nc) pins are also included in the scan register to reserve pins for higher density devices. the x36 configuration has a 70-bit-long register, and the x18 configuration has a 51-bit-long register. the boundary scan register is loaded with the contents of the ram input and output ring when the tap controller is in the capture-dr state and is then placed between the tdi and tdo pins when the controller is moved to the shift-dr state. the extest, sample/preload and sample z instruc- tions can be used to capture the contents of the input and output ring. the boundary scan order tables show the order in which the bits are connected. each bit corresponds to one of the bumps on the sram package. the msb of the register is connected to tdi, and the lsb is connected to tdo. identification (id) register the id register is loaded with a vendor-specific, 32-bit code during the capture-dr state when the idcode command is loaded in the instruction register. the idcode is hardwired into the sram and can be shifted out when the tap controller is in the shift-dr state. the id register has a vendor code and other information described in the identification register definitions table. tap instruction set eight different instructions are possible with the three-bit instruction register. all combinations are listed in the instruction code table. three of these instructions are listed as reserved and should not be used. the other five instruc- tions are described in detail below. the tap controller used in this sram is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented. the tap controller cannot be used to load address, data, or control signals into the sram and cannot preload the input or output buffers. the sram does not implement the 1149.1 commands extest or intest or the preload portion of sample/preload; rather it performs a capture of the inputs and output ring when these instructions are executed. instructions are loaded into the tap controller during the shift-ir state when the instruction register is placed between tdi and tdo. during this state, instructions are shifted through the instruction register through the tdi and tdo pins. to execute the instruction once it is shifted in, the tap controller needs to be moved into the update-ir state. extest extest is a mandatory 1149.1 instruction which is to be executed whenever the instruction register is loaded with all 0s. extest is not implemented in the tap controller, and therefore this device is not compliant to the 1149.1 standard. the tap controller does recognize an all-0 instruction. when an extest instruction is loaded into the instruction register, the sram responds as if a sample/preload instruction has been loaded. there is one difference between the two instructions. unlike the sample/preload instruction, extest places the sram outputs in a high-z state. idcode the idcode instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. it also places the instruction register between the tdi and tdo pins and allows
preliminary cy7c1471v33 cy7c1473v33 cy7c1475v33 document #: 38-05288 rev. *a page 11 of 26 the idcode to be shifted out of the device when the tap controller enters the shift-dr state. the idcode instruction is loaded into the instruction register upon power-up or whenever the tap controller is given a test logic reset state. sample z the sample z instruction causes the boundary scan register to be connected between the tdi and tdo pins when the tap controller is in a shift-dr state. it also places all sram outputs into a high-z state. sample/preload sample/preload is a 1149.1 mandatory instruction. the preload portion of this instruction is not implemented, so the tap controller is not fully 1149.1-compliant. when the sample/preload instructions are loaded into the instruction register and the tap controller is in the capture-dr state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. the user must be aware that the tap controller clock can only operate at a frequency up to 10 mhz, while the sram clock operates more than an order of magnitude faster. because there is a large difference in the clock frequencies, it is possible that during the capture-dr state, an input or output will undergo a transition. the tap may then try to capture a signal while in transition (metastable state). this will not harm the device, but there is no guarantee as to the value that will be captured. repeatable results may not be possible. to guarantee that the boundary scan register will capture the correct value of a signal, the sram signal must be stabilized long enough to meet the tap controller ? s capture set-up plus hold times (t cs and t ch ). the sram clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a sample/preload instruction. if this is an issue, it is still possible to capture all other signals and simply ignore the value of the ck and ck captured in the boundary scan register. once the data is captured, it is possible to shift out the data by putting the tap into the shift-dr state. this places the boundary scan register between the tdi and tdo pins. note that since the preload part of the command is not implemented, putting the tap into the update to the update-dr state while performing a sample/preload instruction will have the same effect as the pause-dr command. bypass when the bypass instruction is loaded in the instruction register and the tap is placed in a shift-dr state, the bypass register is placed between the tdi and tdo pins. the advantage of the bypass instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. reserved these instructions are not implemented but are reserved for future use. do not use these instructions.
preliminary cy7c1471v33 cy7c1473v33 cy7c1475v33 document #: 38-05288 rev. *a page 12 of 26 note: 8. the 0/1 next to each state represents the value at tms at the rising edge of tck. test-logic reset test-logic/ idle select dr-scan capture-dr shift-dr exit1-dr pause-dr exit2-dr update-dr select ir-scan capture-dr shift-ir exit1-ir pause-ir exit2-ir update-ir 0 1 1 0 1 0 1 0 0 0 1 1 1 0 1 0 1 0 0 0 1 0 1 1 0 1 0 0 1 1 1 [8]
preliminary cy7c1471v33 cy7c1473v33 cy7c1475v33 document #: 38-05288 rev. *a page 13 of 26 tap electrical characteristics over the operating range [9, 10] parameter description test conditions min. max. unit v oh1 output high voltage i oh = ? 4.0 ma 2.4 v v oh2 output high voltage i oh = ? 100 a3.0 v v ol1 output low voltage i ol = 8.0 ma 0.4 v v ol2 output low voltage i ol = 100 a0.2v v ih input high voltage 1.8 v dd + 0.3 v v il input low voltage ? 0.5 0.8 v i x input load current gnd < v i < v ddq ? 55 a tap ac switching characteristics over the operating range [11, 12] parameter description min. max. unit t tcyc tck clock cycle time 100 ns t tf tck clock frequency 10 mhz t th tck clock high 40 ns t tl tck clock low 40 ns set-up times t tmss tms set-up to tck clock rise 10 ns t tdis tdi set-up to tck clock rise 10 ns t cs capture set-up to tck rise 10 ns notes: 9. all voltage referenced to ground. 10. overshoot: v ih (ac) < v dd + 1.5v for t < t tcyc /2; undershoot: v il (ac) < 0.5v for t < t tcyc /2; power-up: v ih < 2.6v and v dd < 2.4v and v ddq < 1.4v for t < 200 ms. 11. t cs and t ch refer to the set-up and hold time requirements of latching data from the boundary scan register. 12. test conditions are specified using the load in tap ac test conditions. t r /t f = 1 ns. 0 0 1 2 . . 29 30 31 boundary scan register identification register 0 1 2 . . . . . 0 1 2 instruction register bypass register selection circuitry selection circuitry tap controller tdi tdo tck tms
preliminary cy7c1471v33 cy7c1473v33 cy7c1475v33 document #: 38-05288 rev. *a page 14 of 26 tap timing and test conditions hold times t tmsh tms hold after tck clock rise 10 ns t tdih tdi hold after clock rise 10 ns t ch capture hold after clock rise 10 ns output times t tdov tck clock low to tdo valid 20 ns t tdox tck clock low to tdo invalid 0 ns tap ac switching characteristics over the operating range (continued) [11, 12] parameter description min. max. unit (a) tdo c l = 20 pf z 0 = 50 ? gnd 1.25v 50 ? vih 0v all input pulses test clock test mode select tck tms test data-in tdi test data-out t tcyc t tmsh t tl t th t tmss t tdis t tdih t tdov t tdox tdo
preliminary cy7c1471v33 cy7c1473v33 cy7c1475v33 document #: 38-05288 rev. *a page 15 of 26 identification register definitions instruction field 18 36 x72 description revision number (31:29) 000 000 000 reserved for version number department number (27:25) 101 101 101 department number voltage (28&24) 00 00 00 architecture (23:21) 001 001 001 architecture type memory type (20:18) 001 001 001 defines type of memory device width (17:15) 010 100 110 defines width of the sram. 36 or 18 device density (14:12) 100 100 100 defines the density of the sram cypress jedec id (11:1) 00000110100 00000110100 00000110100 allows unique identification of sram vendor id register presence (0) 1 1 1 indicate the presence of an id register scan register sizes register name bit size (x18) bit size (x36) bit size (x72) instruction 3 3 3 bypass 1 1 1 id 32 32 32 boundary scan tbd tbd tbd identification codes instruction code description extest 000 captures the input/output ring contents. places the boundary scan register between the tdi and tdo. forces all sram outputs to high-z state. this instruction is not 1149.1-compliant. idcode 001 loads the id register with the vendor id code and places the register between tdi and tdo. this operation does not affect sram operation. sample z 010 captures the input/output contents. places the boundary scan register between tdi and tdo. forces all sram output drivers to a high-z state. reserved 011 do not use. this instruction is reserved for future use. sample/preload 100 captures the input/output ring contents. places the boundary scan register between tdi and tdo. does not affect the sram operation. this instruction does not implement 1149.1 preload function and is therefore not 1149.1-compliant. reserved 101 do not use. this instruction is reserved for future use. reserved 110 do not use. this instruction is reserved for future use. bypass 111 places the bypass register between tdi and tdo. this operation does not affect sram operation.
preliminary cy7c1471v33 cy7c1473v33 cy7c1475v33 document #: 38-05288 rev. *a page 16 of 26 boundary scan order (2m 36) tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb boundary scan order (4m 18) tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb tdb
preliminary cy7c1471v33 cy7c1473v33 cy7c1475v33 document #: 38-05288 rev. *a page 17 of 26 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. ? 65 c to +150 c ambient temperature with power applied............................................. ? 55 c to +125 c supply voltage on vdd relative to gnd ...... ? 0.5v to +4.6v dc voltage applied to outputs in high-z state .................................... ? 0.5v to v ddq + 0.5v dc input voltage ................................. ? 0.5v to v ddq + 0.5v current into outputs (low)......................................... 20 ma static discharge voltage.......................................... > 2001v (per mil-std-883, method 3015) latch-up current.................................................... > 200 ma operating range range ambient temperature [13] v dd v ddq com ? l0 c to +70 c 3.3v +5%/ ? 5% 2.375v(min.) v dd (max.) electrical characteristics over the operating range parameter description test conditions min. max. unit v dd power supply voltage 3.135 3.465 v v ddq i/o supply voltage 2.375 v dd v v oh output high voltage v dd = min., i oh = ? 4.0 ma 3.3v 2.4 v v dd = min., i oh = ? 1.0 ma 2.5v 2.0 v v ol output low voltage v dd = min., i ol = 8.0 ma 3.3v 0.4 v v dd = min., i ol = 1.0 ma 2.5v 0.4 v v ih input high voltage 3.3v 2.0 v 2.5v 1.7 v v il input low voltage [14] 3.3v ? 0.3 0.8 v 2.5v ? 0.3 0.7 v i x input load current gnd < v i < v ddq 5 a input current of mode 30 a input current of zz input = v ss 30 a i oz output leakage current gnd < v i < v ddq, output disabled 5 a i dd v dd operating supply v dd = max., i out = 0 ma, f = f max = 1/t cyc 150 mhz tbd ma 133 mhz tbd ma 117 mhz tbd ma 100 mhz tbd ma i sb1 automatic ce power-down current ? ttl inputs max. v dd , device deselected, v in > v ih or v in < v il f = f max = 1/t cyc 150 mhz tbd ma 133 mhz tbd ma 117 mhz tbd ma 100 mhz tbd ma i sb2 automatic ce power-down current ? cmos inputs max. v dd , device deselected, v in < 0.3v or v in > v ddq ? 0.3v, f = 0 all speed grades tbd ma i sb3 automatic ce power-down current ? cmos inputs max. v dd , device deselected, or v in < 0.3v or v in > v ddq ? 0.3v, f = f max = 1/t cyc 150 mhz tbd ma 133 mhz tbd ma 117 mhz tbd ma 100 mhz tbd ma i sb4 automatic ce power-down current ? ttl inputs max. v dd , device deselected, v in > v ih or v in < v il , f = 0 all speed grades tbd ma notes: 13. t a is the case temperature. 14. minimum voltage equals ? 2.0v for pulse durations of less than 20 ns.
preliminary cy7c1471v33 cy7c1473v33 cy7c1475v33 document #: 38-05288 rev. *a page 18 of 26 capacitance [16] parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v dd = v ddq = 2.5v tbd pf c clk clock input capacitance tbd pf c i/o input/output capacitance tbd pf thermal resistance [16] parameter description test conditions bga typ. tqfp typ. unit ja thermal resistance (junction to ambient) still air, soldered on a 4.25 1.125 inch, four-layer printed circuit board tbd tbd c/w jc thermal resistance (junction to case) tbd tbd c/w switching characteristics over the operating range parameter description -150 -133 -117 -100 unit min. max. min. max. min. max. min. max. clock t cyc clock cycle time 6.7 7.5 8.5 10 ns f max maximum operating frequency 150 133 117 100 mhz t ch clock high 2.5 2.5 2.8 3.0 ns t cl clock low 2.5 2.5 2.8 3.0 ns output times t cdv data output valid after clk rise 5.5 6.5 7.5 8.5 ns t eov oe low to output valid [16, 19, 21] 2.5 3.0 3.4 3.8 ns t doh data output hold after clk rise 2.5 2.5 2.5 2.5 ns t chz clock to high-z [16, 17, 19, 20, 21] 3.5 3.8 4.0 4.5 ns t clz clock to low-z [16, 17, 19, 20, 21] 2.5 3.0 3.0 3.0 ns t eohz oe h igh to o utput h igh- z [16, 17, 19, 21] 2.5 3.0 3.5 4 ns t eolz oe low to output low-z [16, 17, 19, 21] 0 0 0 ns set-up times t as address set-up before clk rise 1.5 1.5 1.5 1.5 ns note: 15. the load used for v oh and v ol testing is shown in (b) of the ac test loads. 16. tested initially and after any design or process change that may affect these parameters. 17. unless otherwise noted, test conditions assume signal transition time of 1.5 ns or less, timing reference levels of 1.5v, in put pulse levels of 0 to 3.3v, and output loading of the specified i ol /i oh and load capacitance. shown in (a), (b), and (c) of ac test loads. 18. input waveform should have a slew rate of 2 v/ns. 19. t chz , t clz , t oev , t eolz , and t eohz are specified with ac test conditions shown in part (a) of ac test loads. transition is measured 200 mv from steady-state voltage. 20. at any given voltage and temperature, t eohz is less than t eolz and t chz is less than t clz to eliminate bus contention between srams when sharing the same data bus. these specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. device is designed to achieve high-z prior to low-z under the same system conditions. 21. this parameter is sampled and not 100% tested. output r = 317 ? r = 351 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v l = 1.5v for 3.3v v ddq v ddq all input pulses [18] 3.3v gnd 90% 10% 90% 10% rise time: (c) ac test loads and waveforms 2 v/ns fall time: 2 v/ns = 1.25v for 2.5v v ddq
preliminary cy7c1471v33 cy7c1473v33 cy7c1475v33 document #: 38-05288 rev. *a page 19 of 26 t ds data input set-up before clk rise 1.5 1.5 1.5 1.5 ns t cens cen set-up before clk rise 1.5 1.5 1.5 1.5 ns t wes we , bws x set-up before clk rise 1.5 1.5 1.5 1.5 ns t als adv/ld set-up before clk rise 1.5 1.5 1.5 1.5 ns t ces chip select set-up 1.5 1.5 1.5 1.5 ns hold times t ah address hold after clk rise 0.5 0.5 0.5 0.5 ns t dh data input hold after clk rise 0.5 0.5 0.5 0.5 ns t cenh cen hold after clk rise 0.5 0.5 0.5 0.5 ns t weh we , bw x hold after clk rise 0.5 0.5 0.5 0.5 ns t alh adv/ld hold after clk rise 0.5 0.5 0.5 0.5 ns t ceh chip select hold after clk rise 0.5 0.5 0.5 0.5 ns shaded area contains advanced information. switching characteristics over the operating range (continued) parameter description -150 -133 -117 -100 unit min. max. min. max. min. max. min. max. switching waveforms cen clk address ce we data in/out t cyc t ch t cl t cens t cenh ra1 t ah t as t wes t weh t ces t ceh t cdv q4 q1 = don ? t care = undefined out d2 in d5 in out read write deselect write read read read suspend read deselect deselect wa2 ra3 ra4 wa5 ra6 ra7 t clz t doh q3 out t chz device originally deselected q7 out t chz t cens t cenh t doh q6 out read/write/deselect sequence we is the combination of we and bws x (x = a, b, c, d, e, f, g, h for x72, x = a, b, c, d for x36 and x = a, b for x18) the device. any chip select can deselect the device. rax stands for read address x, wa stands for write address x, dx stands for data-in x, qx stands for data-out x. ce is the combination of ce 1 , ce 2 , and ce 3 . all chip selects need to be active in order to select to define a write cycle (see write cycle description table).
preliminary cy7c1471v33 cy7c1473v33 cy7c1475v33 document #: 38-05288 rev. *a page 20 of 26 switching waveforms (continued) adv/ld clk address ce 1a data in/out t cyc t ch t cl t als t alh ra1 t ah t as t ces t ceh t cdv q1 = don ? t care = undefined out begin read burst read t clz t doh device originally deselected wa2 q1+1 out q1+2 out q1+3 out ra3 t clz t chz d2+1 in d2+2 in d2+3 in d2 in t cdv q3 out t ds t dh burst read burst read begin write burst write burst write burst write begin read burst read burst read burst sequences bws x t wes t weh we t ws t wh out q3+1 the combination of we and bws x (x = a, b, c, d, e, f, g, h for x72, x = a, b, c, d for x36 and x = a, b for x18) ce is the combination of ce 1 , ce 2 , and ce 3 . all chip enables need to be active in order to select the device. any chip enable can deselect the device. rax stands for read address x, wa stands for write address x, dx stands for data-in for location x, qx stands for data-out for location x. cen held low. during burst writes, byte writes can be conducted by asserting the appropriate bws x input signals. burst order determined by the state of the mode input. cen held low. oe held low. define a write cycle (see write cycle description table).
preliminary cy7c1471v33 cy7c1473v33 cy7c1475v33 document #: 38-05288 rev. *a page 21 of 26 switching waveforms (continued) oe three-state i/os oe timing t eohz t eov t eolz ordering information speed (mhz) ordering code package name package type operating range 150 cy7c1471v33-150ac CY7C1473V33-150AC a101 100-lead 14 20 1.4 mm thin quad flat pack commercial cy7c1471v33-150bgc cy7c1473v33-150bgc bg119 119-ball bga (14 22 2.4 mm) cy7c1471v33-150bzc cy7c1473v33-150bzc bb165c 165-ball fbga (15 17 mm) cy7c1475v33-150bgc bg209 209-ball bga (14 22 2.2 mm) 133 cy7c1471v33-133ac cy7c1473v33-133ac a101 100-lead 14 20 1.4 mm thin quad flat pack cy7c1471v33-133bgc cy7c1473v33-133bgc bg119 119-ball bga (14 22 2.4 mm) cy7c1471v33-133bzc cy7c1473v33-133bzc bb165c 165-ball fbga (15 17 mm) cy7c1475v33-133bgc bg209 209-ball bga (14 22 2.2 mm) 117 cy7c1471v33-117ac cy7c1473v33-117ac a101 100-lead 14 20 1.4 mm thin quad flat pack cy7c1471v33-117bgc cy7c1473v33-117bgc bg119 119-ball bga (14 22 2.4 mm) cy7c1471v33-117bzc cy7c1473v33-117bzc bb165c 165-ball fbga (15 17 mm) cy7c1475v33-117bgc bg209 209-ball bga (14 22 2.2 mm) 100 cy7c1471v33-100ac cy7c1473v33-100ac a101 100-lead 14 20 1.4 mm thin quad flat pack cy7c1471v33-100bgc cy7c1473v33-100bgc bg119 119-ball bga (14 22 2.4 mm) cy7c1471v33-100bzc cy7c1473v33-100bzc bb165c 165-ball fbga (15 17 mm) cy7c1475v33-100bgc bg209 209-ball bga (14 22 2.2 mm) shaded area contains advanced information.
preliminary cy7c1471v33 cy7c1473v33 cy7c1475v33 document #: 38-05288 rev. *a page 22 of 26 package diagram 100-pin thin plastic quad flatpack (14 20 1.4 mm) a101 51-85050-*a
preliminary cy7c1471v33 cy7c1473v33 cy7c1475v33 document #: 38-05288 rev. *a page 23 of 26 package diagram (continued) 165-ball fbga (15 17 1.20 mm) bb165c 51-85165-**
preliminary cy7c1471v33 cy7c1473v33 cy7c1475v33 document #: 38-05288 rev. *a page 24 of 26 package diagram (continued) 51-85115-*b 119-lead pbga (14 x 22 x 2.4 mm) bg119
preliminary cy7c1471v33 cy7c1473v33 cy7c1475v33 document #: 38-05288 rev. *a page 25 of 26 ? cypress semiconductor corporation, 2003. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. zero bus latency, no bus latency, and nobl are trademarks of cypress semiconductor corporation. all product and company names mentioned in this document are the trademarks of their respective holders. package diagram (continued) 209-lead pbga (14 x 22 x 2.20 mm) bg209 51-85143-*b
preliminary cy7c1471v33 cy7c1473v33 cy7c1475v33 document #: 38-05288 rev. *a page 26 of 26 document history page document title: cy7c1471v33/cy7c1473v33/cy7c1475v33 2m x 36/4m x 18/1m x 72 flow-through sram with nobl ? architecture document number: 38-05288 rev. ecn no. issue date orig. of change description of change ** 114675 08/06/02 pks new data sheet *a 121521 02/07/03 cjm updated features for package offering updated ordering information changed advanced information to preliminary

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